1. Field of the Invention
This is an improved TTL circuit and more particularly a TTL circuit that is testable by D.C. Testing Techniques.
2. Description of the Prior Art
Transistor-transistor-logic (TTL) circuits are notoriously well-known in the art and it is well-known to place a hundred or more of these circuits on a single semiconductor chip. When a lage number of such circuits are placed on a single semiconductor chip, complex logic functions are achievable even though external contacts can be made only to a limited number of these circuits. Whenever there are inaccessable circuit nodes, testing becomes a problem.
FIG. 1 illustrates one type of prior art circuit in which a TTL circuit is connected as a NAND gate. Assuming that the input terminals A, B, and C, and the output terminal D are not externally accessible, then this circuit can not be completely tested by D.C. Techniques. Specifically, a defect in input transistor T1, such as a base to emitter short circuit, can not be detected. Assuming first that all the logic inputs at terminals A, B, and C are at a logical up level, T1 is cut off and intermediate node X is charged to a logic up level by means of more positive potential V1 through resistor R1 and Schottky barrier diode D1. This up logic level turns output transistor T2 on causing the output terminal D to assume a down logic level such as potential V2 which may be at ground potential. Resistor R2 forms a load resistance for transistor T2 and usually has a value approximately equal to that of R1.
By bringing any one of the input terminals to a down level, node X would also be brought to a down level. Assuming, however, a defect in input transistor T1 such as a base to emitter short circuit, for example, then node X will not be brought down as intended. Rather, over an extended period such as 80 to 100 nanoseconds, the reverse biased Schottky diode D1 (and the reversed biased collector to base junction of T1) will provide sufficient leakage to bring node X to a down level. This in turn will turn off T2 permitting the output D to be charged to an up level through resistor R2. For this reason, a correct output condition will be indicated after 80 to 100 nanoseconds even though a defect is present in transistor T1. Such a defect can only be detected by an A.C. test which will note that the gate has not switched in the customary time (approximately 7 nanoseconds). A.C. Testing, however, is expensive, time consuming, and generally impractical for a high volume manufacturing operation.
A second type of prior art circuit is illustrated in FIG. 2. FIG. 2 includes all the elements of FIG. 1 and has been correspondingly labeled with reference numerals. It is noted that FIG. 2 further includes resistor R3 which is connected to the path coupling transistors T1 and T2. In order to optimize power/performance characteristics in the FIG. 2 prior art embodiment, it is customary to set the values of resistors R1 and R3 equal to each other and twice the resistance value of R2. Thus, whereas in the FIG. 1 embodiment, R1 and R2 might typically be set around 3 K ohms, in the FIG. 2 embodiment only R2 would be set equal to 3 K ohms. Resistors R1 and R3 would be set equal to approximately 6 K ohms.
Thus, even though the FIG. 2 prior art circuit is D.C. testable, it occupies a significantly larger area on a semiconductor chip. Not only is an additional resistor R3 required, but the need for larger resistances further increases the area requirements. Moreover, since a higher resistance dissipates more heat, in the case of high power circuits, for comparable current levels additional power consumption and cooling must be considered. In the illustrated NPN technology of FIG. 2, the resistors are customarily formed in the P-type "base" diffusions having a resistivity of approximately 180 ohms per square. Once the resistivity of the material has been established, the resistance of a particular resistor is determined by its dimensions of length and width. Resistors are made as narrow as the yield tolerances allow so that length becomes the dimension by which resistance can be adjusted. Therefore, not only will the additional resistor R3 take up extra room, but it as well as formerly smaller resistance R1 will be significantly longer than R2. Although there are known techniques for increasing resistance in as limited an area as possible, such as running a resistor in a serpentine pattern or various "pinch" resistor techniques, these all take up additional space over the prior art circuit illustrated in FIG. 1.
Accordingly, the prior art circuit of FIG. 1 has advantages over the prior art circuit of FIG. 2, together with the one significant disadvantage that it is not testable by D.C. techniques.